Dual modulus counter for use in a phase locked loop

ABSTRACT

In a phase locked loop having a variable divider, a dual modulus counter is used to provide the variable divider with selection signals. The variable divider is capable of providing an overall division ratio in increments of one over a contiguous range of values. The dual modulus counter includes a counter, a comparator and logic gates which generate selection signals that allow the variable divider to divide an input signal by at least division ratios R1 and R2. A phase locked loop utilizing the dual modulus counter is particularly well suited for use in a digital frequency synthesizer.

FIELD OF THE INVENTION

The present invention relates generally to a programmable divider foruse in a digital frequency synthesizer. More particularly, the inventionrelates to a dual modulus counter suitable for controlling theprogrammable divider.

BACKGROUND OF THE INVENTION

In digital frequency synthesizers, there is a need for a variabledivider which counts the cycles of an input signal having a givenfrequency until a predetermined number of counts have been accumulated.The size of the count is usually referred to by the letter N. Once Ncounts have been accumulated, the variable divider is reset to begin thecycle again. It is desirable for the number of counts N to be variablein order that it can be programmed in advance of each count by means ofa control input.

When N is large and the operating frequency of the counter is to behigh, technical difficulties can arise in constructing a multistage highfrequency variable divider. In the prior art, the problem is typicallyovercome by using a fixed high frequency divide by M stage prior to avariable divide by N stage. This solution is not always desirablebecause the total division factor can only be a multiple of M.

In a digital frequency synthesizer application, it is usually desirableto be able to program the total division factors in steps or incrementsof 1. The steps, therefore, relate to the frequency resolution or thefrequency step size of the synthesizer. If the divider is onlyprogrammable in steps of M, the frequency steps available are relativelycoarse and determined by the factor M.

Another approach to the problem is to begin with a high frequencydivider stage or prescaler while retaining the ability to program thedivider count cycle length in steps of 1. This arrangement allows theprescaler to be varied between dividing ratios of R and R+1.

It is possible, for example, for a dual ratio prescaler having thedivision ratios 10 and 11 to perform a division of 157. The number 157can be expressed by the equation 7×11+(15-7)×10. The prescaler is firstprogrammed to divide by 11, and the lower frequency divider stage is setto count 7 prescaler output pulses. After counting 7 prescaler outputpulses, the prescaler is set to divide by 10. The low frequency dividerstage is then set to count 8 prescaler output pulses. Upon completion ofthis count, a total of 7×11+8×10=157 input pulses have been applied tothe prescaler input. The cycle is then begun again. It should be notedthat in order to obtain numbers in steps of 1, the number of times theprescaler divides by 11 must be programmed from 0 to 9 and the number of10's in the total number must not be less than 9. This relationship setsa lower bound of R(R-1) for the contiguous number range that can beachieved with a two ratio prescaler having ratios R and R+1.

The most common method employed to count two different numbers ofprescaler output pulses, N1 and N2, while the prescaler is dividingrespectively by ratios R1 and R2, is to use two separate low frequencydown counters that are preset to the values N1 and N1+N2, respectively.For example, the division of 157 with the aid of a 10/11 prescaler couldbe achieved by presetting one divider to N=7 and the other to N1+N2=15.The prescaler would then first be set to divide by R1(11) while both lowfrequency counters counted down on the prescaler output pulses. When theN1 counter reaches zero after 7 prescaler output pulses, the prescalerwould switch and divide by 10, and the N2 counter would continue tocount down a further 8 prescaler output pulses until it reaches zero,completing the cycle. This system has the advantage that a desireddivision number is simply expressed in values to which the N1 and N2counters can be preset. This arrangement has the disadvantage that twovariable dividers are required and power consumption is increased whenboth dividers are operating. Increased power consumption is asignificant disadvantage for battery powered equipment.

U.S. Pat. No. 4,053,739 describes a single variable divider that isalternatively programmed with the value N1 when the prescaler divides bythe value R1 and is programmed with the value N2 when the prescalerdivides by the value R2. This device has the advantage that a singlevariable divider suffices. Unfortunately, the described arrangementincludes additional circuit complexity in the form of a multi-lineswitch. The multi-line switch alternately selects the bits correspondingto the values N1 and N2 in order to preset the single variable divider.Although this additional circuitry operates at a lower power consumptionthan a circuit having two variable dividers, it still requiressubstantially the same amount of circuitry when implemented as anintegrated circuit.

Accordingly, there is a need for a counter for a programmable dividerwhich can register both the counts N1 and N2 without them beingpresented alternately to the counter. This arrangement would eliminatethe need for a complex multi-line switch.

SUMMARY OF THE INVENTION

The present invention relates to a circuit and method for controlling aprogrammable divider for use in a digital frequency synthesizer. Theprogrammable divider is responsive to a dual modulus counter. The dualmodulus counter includes a preloadable binary counter, a comparator andlogic gates which generate selection signals to control the programmabledivider. The preloadable counter is loaded with a value N1. The countercounts to a predetermined intermediate value such as zero and generatesan output signal. The counter then continues to count until it reaches asecond value N2. The comparator compares the output of the counter tothe value N2 which was loaded into the comparator. When the binarycounter reaches the value N2, the comparator generates a second outputwith is applied to the logic gates. The logic gates generate theselection signals which cause the programmable divider to divide aninput signal by the division ratios R1 or R2. In a first embodiment ofthe present invention, the binary counter is a down counter. In a secondembodiment of the present invention, the binary counter is an upcounter. The dual modulus counter of the present invention may also beused to control more than one programmable divider. The presentinvention is particularly well suited for use in a digital frequencysynthesizer of the type having a phase locked loop.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of the first embodiment of the presentinvention having a binary down counter;

FIG. 2 is a schematic diagram of a second embodiment of the presentinvention having a binary up counter;

FIG. 3 is a schematic diagram of the dual modulus counter of the presentinvention controlling two programmable dividers; and

FIG. 4 is a schematic diagram of a phase locked loop utilizing avariable divider.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a schematic diagram of the first embodiment of thepresent invention. In the first embodiment, there is shown a dualmodulus counter having a binary down counter 12 which is loaded at thebeginning of a count sequence with the value N1. There is a prescaler 11which can divide by the ratios R1 or R2. The output pulses of theprescaler 11 decrement the down counter 12 until the down counterreaches the value zero. When the down counter 12 reaches zero, itgenerates an output pulse which sets a latch 14. The setting of thelatch 14 causes the prescaler 11 to switch to its alternative divisionratio R2. The output pulses of the prescaler 11 continue to decrementthe down counter 12 until a comparator 13 detects that it has reachedthe state corresponding to a value -N2. When the comparator 13 detectsthe value -N2, the latch 14 is already set, and both inputs to an ANDgate 15 are enabled. The AND gate 15 then generates an output signalwhich is clocked into a d-type flip flop 16 upon the next prescaleroutput pulse. The latch 14 is then reset, and the down counter 12 can bereloaded with the value N1, while the prescaler 11 resumes division bythe ratio R1.

Since the inputs to the AND gate 15 are no longer enabled because thelatch 14 has been reset, the output signal at the AND gate 15 willdisappear and this state will be transferred into the d-type flip flop16 upon the next output pulse of the prescaler 11. The preset controlsignal to the down counter 12 is removed leaving it loaded with thevalue N1 and ready for the next count sequence. The total number ofprescaler input pulses in the count sequence, therefore is expressed bythe equation N_(TOT) =(N1+1)R1+(N2+1)R2. In order to obtain a desiredN_(TOT), it is necessary to subtract the excess R1+R2 value from thedesired number. For example, if R1=11 and R2=10, and a total divisioncycle length of 170 is desired, 10+11=21 is first subtracted from 170resulting in the value 149. N1 must then be 9 and N2=14-9=5. In order toavoid impossible negative values of N2 arising, a desired count N mustsatisfy the following equations:

    INT {(N-R1-R2)/R2}≧|N-R1-R2|.sub.R2

    INT {(N-R1-R2)/R1}≧|N-R1-R2|.sub.R1

The expression INT (x) means the whole number part of x, i.e., ifx=5.3667, then INT(x)=5. This is an expression of the above-describedlower bound on the contiguous number range that can be spanned using thedual ratio prescalers associated with the present invention.

In the circuit illustrated in FIG. 1, there is no restriction placed onthe relative magnitudes of N1 and N2. The word length of the comparator13 was the same as the whole number in the counter 12. However, to covera range of values of N in steps of 1 with no gaps only requires thatN1+1 take on values between 1 and R1-1 i.e., the range of the leastsignificant digit of N modulo R1. Since this range is often much shorterthan the total length of the counter 12, the comparator 13 word lengthcan be advantageously reduced. The reduction of the word length of thecomparator 13 can be achieved by using an up counter.

Referring now to FIG. 2, a second embodiment of the present inventionusing an up counter is illustrated. In the second embodiment of thepresent invention, there is a preloadable binary up counter 22 that isresponsive to the output of a prescaler 21. The prescaler 21 is capableof dividing by division ratios R1 or R2. The up counter 22 is initiallypreset to a value -N1, while the prescaler 21 is initially set to divideby R1. The output pulses of the prescaler 21 increment the up counter 22until the output of the up counter reaches all logical ones. When theoutput of the up counter 22 is all logical ones instead of all logicalzeros, the output can be more rapidly detected.

Upon detecting all logical ones, a latch 24 is set causing the prescaler21 to switch to division by the ratio R2. If N2 equals 111..1, an L-bitcomparator 23 provides an output signal to an AND gate 25. The AND gate25 generates an output signal. Otherwise the L-bit comparator 23generates an output signal after one further output pulse from theprescaler 21 if N2=0, after two output pulses if N2=1, etc. On theimmediately following prescaler output pulse, the output of AND gate 25is clocked into a d-type flip flop 26 causing the latch 24 to be reset.The prescaler 21 returns to dividing by R1, and the up counter isreloaded with the value -N1. Since the resetting of the latch 24 removesone of the enabling inputs to the AND gate 25, the output of the ANDgate becomes 0. This output is transferred to the d-type flip flop 26 onthe next prescaler output pulse, thereby removing the reload controlsignal to the up counter 22 and leaving it in the state -N1 and leavingit ready to repeat the entire cycle.

The total number of prescaler input clock pulses in a complete divisioncycle for the circuit of FIG. 2 is defined by the equationN=N1×R1+(N2+2)×R2. It should be noted, however, that the value N2=-1 iscorrectly treated by the circuit, so that N2 is considered to rangethrough the values -1, 0, +1 . . . to 2**L-2. The value N2' is definedby the equation N2'=N2+1 and ranges from the value 0 to 2^(L) -1. Thevalue N is defined by the equation N=N1×R1+N2'×R2+R2. The values for N1and N2' may be calculated as follows: (1) Subtract the excess R2 from Nto get N', (2) calculate N2' as the remainder upon division of N' by R1,(3) calculate N1 as the integer part of N'/R1-N2', and (4) applyN2=N2'-1 to the L-bit comparator 23 and N1 to the divider preload inputof counter 22. These manipulations can be performed more simply if thevalue R1 is a power of 2.

Referring now to FIG. 3, a schematic diagram illustrates a plurality ofprogrammable dividers or prescalers 30, 31 being controlled by the dualmodulus counter of the present invention. Two digital comparators 35, 36are used to examine the state of the least significant L-bits of a maincounter 37. After counting up from a value -N1 to an all logical onescondition, the comparators 35, 36 in turn detect when the leastsignificant bits of the main counter 37 becomes equal to N2 and then tothe value N3. These events cause the prescalers 30 and 31 respectivelyto divide by their alternative ratios.

For example, suppose the prescaler 31 has the ratios 10 and 11available, while the prescaler 30 has ratios of 9 and 10 available.Assuming that the flip flops 38, 39 and 40 are in the reset condition,both prescalers 30, 31 begin by dividing by 10. The counter 37 thencounts up from -N1 until its output is all logical ones. The latch 38then becomes set, causing the prescaler 31 to divide by 11. The counter37 continues to count up until the comparator 36 detects a statecorresponding to the value N2. If latch 38 is also set, both inputs toan AND gate 41 are enabled and the latch 39 is set. This causes theprescaler 30 to begin dividing by 9 while the prescaler 31 continues todivide by 11. The counter 37 continues to count until the comparator 35detects a bit state corresponding to the value N3. At this point, iflatch 39 is already set, both inputs to the AND gate 42 are enabled andupon the next output pulse from the prescaler 31 the output signal ofthe AND gate 42 is clocked into the flip flop 40, causing the latches38, 39 to be reset and the reloading of the main counter 37 to thestarting state N1. The prescalers 30, 31 are now back in their originaldivide by 10 condition, and the inputs to the AND gate 42 are no longerenabled. After one more pulse from the prescaler 31, the zero signalfrom the AND gate 42 is transferred into the flip flop 40 removing thereset condition and leaving the counter 37 in the state -N1 and ready tostart a new cycle.

The total cycle length in terms of output pulses of the input clocksignal F_(c) can be expressed by the following equation:

    N=100N1+110(N2+1)+99(|N3-N2|+1)

where the absolute value of N3-N2 corresponds to modulo 2**L, where L isthe number of least significant bits of the counter 37 examined by thecomparators 35, 36. The value N3' is defined by the equation N3'=N3-N2.The value of N, therefore, can be defined by the following equation:

    N=100(N1+N2)+110(N2+1)+10N2-N3'+209

A desired count may be produced in the following fashion, (1) subtractthe excess 209 from the desired count, getting N', (2) round up N' tothe next multiple of 10, which is called N", (3) set N3' to (N"-N'), (4)set N2 to the 10's digit of N", and (5) set N1 to the 100's digit ofN'-N2. For example, suppose N=1,568. Then N'=1,568-209=1,359. N"=1,360.N3'=N"-N'=1. N2=6(10's digit of N"). N1=13-N2=7(100's digit N"-N2).Because of the subtraction of N2 from the number of 100's in N" and thevalue of N2 ranges up to 9, the number of 100's in N" can not be lessthan 9. Therefore the lower bound on the contiguous number range is ofthe order 900+(209-9)=1,100. This is an order of magnitude lower thanthe lower bound of 9,900 that would apply for a two-ratio prescaler ofratios 100 and 101. In general, an advantageous way to obtain a totalfrequency reduction of the order of R**2 from the input clock signalF_(c) to the input of the low frequency divider is to use two prescalershaving the ratios (R, R+1) and (R, R-1) respectively.

The principles of the present inventions may be extended by addingadditional comparators as necessary. The comparators are not constrainedto be of the same word length and bits, nor are the prescalers theycontrol constrained to exist separately. The two prescalers 30, 31 ofFIG. 3 can also be regarded as a single circuit having three or moredivision ratios selectable by two or more control lines. Such anarrangement can be advantageous because the exact moment at which thehighest frequency prescaler 30 is switched between its ratios can bemore time critical than the lower frequency logic can define. It is,therefore, possible that a necessary precaution is to retime the controlsignal to the highest frequency prescaler with the logic havingsubstantially the same speed as prescaler 31. The control signal fromthe low speed logic, therefore, should preferably pass through themedium speed prescaler 31 to be retimed more accurately. This will havea small penalty on the lower bound of the contiguous number range thatthe overall division ratios can span, but it will increase the maximumfrequency of operation before timing problems are encountered.

The prescaler division ratios of the present invention are notconstrained to any particular values. Common values that simplify thecalculation of the values N1, N2, and N3 can be based on either adecimal number system or a binary number system. In cases where the easeof calculation is not an issue such as when adequate microprocessorcapability exists for number radix manipulations or when precomputedlookup tables can be used, it may be possible to find other advantageouscombinations of prescaler ratios, e.g. noncommensurate primes.

Referring now to FIG. 4, a schematic diagram illustrates the use of thepresent invention in a phase locked loop. The phase locked loop includesa voltage controlled oscillator 50 which provides an output signal F₀.The output signal F₀ is applied to a variable divider circuit 51. Thevariable divider circuit 51 includes a programmable divider and the dualmodulus counter of the present invention. The total division ratio N ofthe variable divider circuit 51 is a function of the values N1 and N2associated with the dual modulus counter. The output of the variabledivider circuit 51 is a divided output signal F₀ /N which is applied toa phase comparator 52. The phase comparator 52 compares the phase of thedivided output signal F₀ /N to a divided reference frequency signalF_(r) /M. The divided reference frequency signal is produced from areference clock signal that is divided by a digital divider 53. Theoutput of the phase comparator 52 is a signal representative of thephase error. The phase error signal is applied to a loopfilter/integrator 54. The filtered and integrated output is then appliedto the voltage controlled oscillator 50.

While the invention has been described in its preferred embodiments, itis to be understood that the words that have been used are words ofdescription rather than of limitation and that changes within thepurview of the appended claims may be made without departing from thetrue scope and spirit of the invention in its broader aspects.

I claim:
 1. A variable ratio frequency divider circuitcomprising:programmable dividing means, having division ratios R1 andR2, for dividing an input signal into a divided output signal; countingmeans, having a relatively long word length, responsive to apredetermined value N1 and the divided output signal of the programmabledividing means, for generating a plurality of outputs including apredetermined intermediate output; first comparing means, having arelatively short word length, for comparing the output of said countingmeans to a second predetermined value N2 and for generating an outputwhen the output of said counting means corresponds to the value N2; andlogic means, responsive to said counting means and said comparing means,for generating selection signals for the programmable dividing meanssuch that the programmable dividing means divides the input signal bythe ratio R1, N1 times and by the ratio R2, N2 times.
 2. A variableratio frequency divider circuit according to claim 1 wherein saidcounting means is a binary up counter and the intermediate output is alllogical ones.
 3. A variable ratio frequency divider circuitcomprising:programmable dividing means, having division ratios R1 andR2, for dividing an input signal into a divided output signal; countingmeans, responsive to a predetermined value N1 and the divided outputsignal of the programmable dividing means, for generating a plurality ofoutputs including a predetermined intermediate output; first comparingmeans for comparing the output of said counting means to a secondpredetermined value N2 and for generating an output when the output ofsaid counting means corresponds to the value N2; logic means, responsiveto said counting means and said comparing means, for generatingselection signals for the programmable dividing means such that theprogrammable dividing means divides the input signal by the ratio R1, N1times and by the ratio R2, N2 times; second programmable dividing meanshaving division ratios R3 and R4, for dividing the input signal; andsecond comparing means for comparing the output of said counting meansto a third predetermined value N3 and for generating an output when theoutput of said counting means corresponds to the value N3.
 4. A variableratio frequency divider circuit comprising:programmable dividing means,having division ratios R1 and R2, for dividing an input signal into adivided output signal; counting means, responsive to a predeterminedvalue N1 and the divided output signal of the programmable dividingmeans, for generating a plurality of outputs including a predeterminedintermediate output, wherein said counting means is a binary downcounter and the intermediate output is zero; first comparing means forcomparing the output of said counting means to a second predeterminedvalue N2 and for generating an output when the output of said countingmeans corresponds to the value N2; and logic means, responsive to saidcounting means and said comparing means, for generating selectionsignals for the programmable dividing means such that the programmabledividing means divides the input signal by the ratio R1, N1 times and bythe ratio R2, N2 times; wherein said logic means includes first latchingmeans responsive to said counting means; an AND gate responsive to saidfirst latching means and said first comparing means; and second latchingmeans responsive to said AND gate and said divided output signal.
 5. Avariable ratio frequency divider circuit according to claim 2 whereinsaid logic means includes first latching means responsive to saidcounting means; an AND gate responsive to said first latching means andsaid first comparing means; and second latching means responsive to saidAND gate and said divided output signal.
 6. A variable ratio frequencydivider circuit according to claim 3 wherein said logic means includes afirst latching means responsive to said counting means; a first AND gateresponsive to said first latching means and said first comparing means;second latching means responsive to said first latching means and saidfirst AND gate; a second AND gate responsive to said second latchingmeans and said second comparing means; and third latching meansresponsive to said second AND gate and the divided output signal.
 7. Amethod of using a single digital counter with a limited maximumoperating frequency to control a preceding higher frequency stage havingtwo available division ratios R1 and R2, which comprises the stepsof:counting from a value N1 having a relatively long word length whichis determined by an initial state to which the digital counter is set,while the preceding higher frequency stage is set to divide by R1;reaching a conveniently detectable state, such that the preceding higherfrequency stage has divided by R1, N1 times; changing the division ratioto a value R2 after reaching the conveniently detectable state; andcontinuing to divide by the ratio R2 until the digital counter isdetected by a comparator to have reached a state corresponding to thevalue N2 having a relatively short word length such that the precedinghigher frequency stage divides by the ratio R2, N2 times.
 8. A methodaccording to claim 7 which further includes the step of varying thevalues of N1 and N2 such that the overall division ratio N varies insteps of one over a range of contiguous values.
 9. A method of using asingle digital counter of limited maximum frequency to control at leastone preceding higher frequency stage that is set to divide by integerratios which comprises the steps of:setting the digital counter to astarting state having a relatively long word length; comparing the stateof the digital counter to a plurality of states including a state havinga relatively short word length in a digital comparator in order todetect when the digital counter has reached a desired state; selectingbetween the integer ratios when the digital counter has reached thedesired state; registering the desired state in logic means; controllingthe selection of the integer ratio used by the preceding higherfrequency stage in accordance with the state of the logic means; andresetting the logic means to its starting state and the digital counterto its starting state in order to repeat the sequence.
 10. A methodaccording to claim 9 which further includes the step of varying thestates of the digital counter and the comparator such that an overalldivision ratio N is varied continuously in steps of one over a range ofvalues.
 11. A phase locked loop comprising:a voltage controlledoscillator for generating an output; variable dividing means fordividing the output of said voltage controlled oscillator, said variabledividing means including;programmable dividing means having divisionratios R1 and R2, for dividing an input signal into a divided outputsignal; counting means, responsive to a predetermined value N1 having arelatively logic word length and the divided output signal of theprogrammable dividing means, for generating an output including apredetermined intermediate output; comparing means for comparing theoutput of said counting means to a second predetermined value N2 havinga relatively short word length and for generating an output when theoutput of said counting means corresponds to the value N2; and logicmeans, responsive to said counting means and said comparing means, forgenerating selection signals for the programmable dividing means suchthat the programmable dividing means divides the clock signal by theratio R1, N1 times and by the ratio R2, N2 times; and phase comparisonmeans for comparing the divided output signal of said variable dividingmeans to a reference signal to generating a phase error signal which sisupplied to said voltage controlled oscillator.
 12. A phase locked loopaccording to claim 11 which further includes means for filtering thephase error signal and means for integrating the phase error signal. 13.A phase locked loop according to claim 12 which further includesdividing means for dividing the reference signal prior to itsapplication to said phase comparison means.
 14. A variable ratiofrequency divider circuit comprising:a plurality of programmabledividing means, having division ratios R1 to Rq, for dividing an inputsignal into divided output signals; counting means, responsive topredetermined values N1 to Nq and the divided output signals of theprogrammable dividing means, for generating a plurality of outputsincluding a predetermined intermediate output; a plurality of comparingmeans for comparing the output of said counting means to predeterminedvalues of N and for generating an output when the output of saidcounting means corresponds to the value Nq; and logic means, responsiveto said counting means and said comparing means, for generatingselection signals for the programmable dividing means such that theprogrammable dividing means divides the input signal by the ratios R1 toRq.